Multi-phase, low-noise clock synthesizers are critical for optimizing the performance of high-speed serial transceivers. Traditionally, these synthesizers employ LC-oscillator-based phase-locked loops (PLLs). However, integrating multiple LC oscillators in multi-lane transceivers and generating the required multi-phase signals poses significant challenges. While ring oscillators (ROs) provide a viable alternative for generating multiple phases, they suffer from poor phase accuracy and increased sensitivity to supply noise, especially at frequencies beyond 10 GHz. In this seminar, we will explore techniques to improve the phase noise performance and supply noise immunity of RO-based PLLs operating above 10 GHz. Key design strategies include implementing a type-III supply-regulated architecture to extend the frequency range and reduce supply sensitivity. Experimental results from prototype PLLs fabricated in the Intel16 process demonstrate an operating range from 7 to 14 GHz, low phase noise with jitter below 70 fs r.m.s., and impressive supply noise rejection exceeding 30 dB.