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Yiran Chen
Event Speaker
Yiran Chen
Event Speaker Description
John Cocke Distinguished Professor of Electrical and Computer Engineering
Duke University
Event Type
Colloquium
Date
Event Location
BEXL 207
Event Description

The advancement of Artificial Intelligence (AI) and its rapid deployment on a broad spectrum of platforms relies on both design quality and design efficiency of circuits, systems, and algorithms. Moreover, security and robustness concerns arise at both hardware and software levels in some critical applications of AI models. Cross-layer optimization becomes essential to achieve these goals. In this talk, we first introduce circuit-level innovations for emerging AI models and devices, including the popular processing-in-memory (PIM) computing primitives centered on various new types of nanodevices. After that, we discuss efficient architecture design atop these innovations, such as multiplier array, systolic array, PIM-based deep neural network (DNN), and spiking neural network (SNN) pipelines. Then we present hardware-friendly model compression techniques to optimize the quality-efficiency trade-off on AI models. We also introduce several efficient distributed learning frameworks that enable the scalability of AI systems. Finally, we show some approaches to resolve the challenges introduced by the imperfect characteristics of semiconductor devices and automate the designs. We hope our talk will offer the audience a comprehensive overview of a full-stack design and optimization of efficient AI circuits and systems (AI-CAS) solutions.

Speaker Biography

Yiran Chen is the John Cocke Distinguished Professor of Electrical and Computer Engineering at Duke University. He serves as the principal investigator and director of the NSF AI Institute for Edge Computing – Athena, the NSF Industry-University Cooperative Research Center for Alternative Sustainable and Intelligent Computing (ASIC), and the co-director of the Duke Center for Computational Evolutionary Intelligence (DCEI). Dr. Chen is the author of over 600 publications and holds 96 US patents. His works have been recognized with numerous awards and honors, including the IEEE Circuits and Systems Society's Charles A. Desoer Technical Achievement Award and the IEEE Computer Society's Edward J. McCluskey Technical Achievement Award. He is a Fellow of AAAS, ACM, IEEE, and NAI, and the inaugural Editor-in-Chief of IEEE Transactions on Circuits and Systems for Artificial Intelligence (TCASAI).