The trend towards 3DIC construction is driving for much more aggressive interconnect pitch scaling relative to historical trends. As a result, many of the test and assembly manufacturing collaterals are facing technical & economic headwinds, and a new approach is needed to enable a capable & cost-effective manufacturing process. One such collateral is the probe card used during wafer test to interface between the tester and the device under test. This presentation will cover the scalability challenges with current probe card manufacturing processes, and propose a new probe architecture and method of manufacturing that will scale to ultra-fine pitch regime with a significantly improved cost structure. The presentation will also highlight the technical challenges with the proposed manufacturing process that require an interdisciplinary problem-solving approach.
Pooya Tadayon is an Intel Fellow and Director of Assembly & Test Pathfinding within Intel’s Technology Development group. His responsibilities include defining Intel’s packaging and test roadmap, and delivering the building blocks required to enable the roadmap. His current focus is on advanced packaging technologies to enable 2.5/3D ICs and assembly/test solutions for co-packaged photonics that can scale to high volume. Prior to his current role, he was Director of Test Pathfinding from 2011-2018 and Director of Test Technology Integration from 2006-2011. He currently holds 30 patents, with more than three dozen pending, spanning the fields of test interconnect technology, thermal technology, and package/product architecture. Pooya received a B.S. degree in chemistry from the University of Washington in 1993 and a Ph.D. degree in physical chemistry from Oregon State University in 1998.