Thin-Film Transistor Accumulation-Mode Modeling

Event Speaker
John F. Wager
Professor Emeritus, School of Electrical Engineering and Computer Science, Oregon State University
Event Type
Event Location
KEC 1007 or Zoom:
Event Description

Analytical equations are developed for electrostatic assessment of accumulation-mode thin-film transistors (TFTs) so that potential, electric field, and accumulation layer free electron concentration profiles may be generated. Additionally, equations are derived for plotting TFT trap density versus surface potential, based on accurate extraction of the channel mobility as a function of gate voltage. A key factor in formulating these device physics equations is distinguishing between a ‘long-base’ or ‘short-base’ channel thickness. A ‘long-base’ (‘short-base’) channel thickness is defined to occur when the accumulation layer thickness (as calculated in the normal manner) is less than (greater than) the physical thickness of the channel layer. The electrostatic equations derived herein are applied to the analysis of two amorphous oxide semiconductor (AOS) TFTs with differing channel layers, i.e., a 40 nm amorphous indium gallium zinc oxide (a-IGZO) or a 7 nm amorphous indium zinc oxide (a-IZO). Application of these equations suggests that optimal TFT performance is obtained when the channel layer thickness is chosen to be similar to its Debye length. Estimated trap densities of these two AOS TFTs are found to be quite similar. Therefore, the superior mobility performance of the a-IZO TFT compared to the a-IGZO TFT is ascribed to the smaller effective mass of a-IZO, assuming that the maximum (no trapping) drift mobility in the channel is established by the thermally-limited diffusive mobility.

Speaker Biography

Prior to his January 2018 retirement, John F. Wager held the Michael and Judith Gaulke Endowed Chair in the School of EECS at Oregon State University. He is lead author of a book entitled ‘Transparent Electronics.’ Transparent electronics technology developed in his group at OSU was licensed to Hewlett-Packard Company who continued advanced joint-development with his group. This technology is finding emerging, high-value applications in flat-panel display thin-film transistor backplanes.