[Eecs-news-links] Kepler Hiring Intern/Fulltime/part-time positions

Batten, Tina tina.batten at oregonstate.edu
Mon May 13 21:29:18 PDT 2019


Summary
Kepler Computing (A startup founded by a team of ex Intel Vets, and renowned scientists, focusing on  AI, and on extending Moore’s law) is looking for an intern, part-time or full-time candidate to work on  modeling and simulations for an exciting new device. As a Mixed Signal, and Analog engineer on the  team, you will be exposed to various aspects  of circuit design, including Modeling of new device  features in SPICE and Verilog, Circuit Simulations, and layout, using Foundry PDK (65-28 or 10nm), and  Cadence tools.

Responsibilities
● Modeling of new Device Behavior in Spice, and VerilogA to interface with Cadence tool.
● Design of new novel logic circuits & Memory architecture using the modelled behavior in  Cadence.
● Design optimization to optimize circuits for power, and performance.
● Work through layout process, estimate/extract parasitic for circuit behavior modelling.

  Qualifications
● Student must have completed some analog/mixed-signal circuit design course work.
● Should be well versed with Cadence Analog Design Suits towards Design, and Simulations.
● Should have some experience in VerilogA, and Spice Modeling.
● Self-motivated with good communication skills.

About Kepler
We at Kepler are working towards full-stack Design towards next generation compute, that focuses on  AI workloads and enables hardware solutions to accelerate performance.

Mode of communication
Interested Students should please send an email to  rajeev.dokania at keplercompute.com

Work Authorization/Visa Requirement
1.) Ideal Candidate, would be one who is on OPT/CPT Visa, or requires no Work Authorization (US  Citizen/ Permanent Resident).    2.) Contract and Remote Options are available

Compensation
-Will be discussed post interview/selection.
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