[Eecs-news-links] IP Design Engineer @ Praesum Communications (Corvallis)

Batten, Tina tina.batten at oregonstate.edu
Tue Jan 22 10:15:22 PST 2019

We are seeking an Intellectual Property (IP) Design Engineer to become an integral part of our team at our new design center located in Corvallis Oregon. You will be responsible for designing and implementing IP cores for high performance computing applications.


*         Implement IP cores in SystemVerilog
*         Develop and execute test plans to check functionality, compliance, and performance
*         Target cores to FPGAs and perform hardware testing
*         Work with Tech Pubs to document design for customers


*         BSEE or better in Electrical or Computer Engineering
*         Familiarity with architectural specifications
*         Ability to write RTL and test environments in SystemVerilog
*         Ability to write diagnostics and drivers in 'C' in a Linux environment
*         Familiarity with high speed serial transceiver technologies
*         Strong troubleshooting and critical thinking skills
*         Strong attention to detail

If interested, please send a resume to Kent Dahlgren at kent at praesum.com.<mailto:kent at praesum.com>

From: kent at praesum.com<mailto:kent at praesum.com> <kent at praesum.com<mailto:kent at praesum.com>>
Sent: Thursday, January 17, 2019 11:36 AM
To: Tina.Batten at oregonstate.edu<mailto:Tina.Batten at oregonstate.edu>
Cc: kent at praesum.com<mailto:kent at praesum.com>; tina at praesum.com<mailto:tina at praesum.com>; paul at praesum.com<mailto:paul at praesum.com>
Subject: Praesum Communications Intro

Hi Tina

Thanks for reaching out to me yesterday. As you have heard we are planning to move the company up to Oregon. This will occur in two phases: first open an R&D office and then relocate myself and others later.

First some background on Praesum Communications. Praesum was founded in 2000 and has been providing Intellectual Property (IP) cores that implement the RapidIO standard.


We also do consulting in the following areas:

  *   Protocol architecture: We defined the Aurora protocol for Xilinx, the SerialLite III protocol for Altera/Intel and the RapidIO Data Streaming Logical Layer.
  *   Embedded high performance computing (HPEC) using OpenCL. This includes board ports of the runtime as well as kernel development and optimization.
  *   In-memory computing architectures and coherency semantics.


We are interested in hiring engineers to help roll out our next generation switching architecture which supports high performance switching with aggregate switching capacity up to 10 terabits. I have attached a job description for this opportunity.


Kent Dahlgren

Praesum Communications
3558 Round Barn Blvd.
Suite 200
Santa Rosa, California 95403

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