[Eecs-news-links] Job opening at Synopsys
tina.batten at oregonstate.edu
Thu Feb 2 20:44:33 PST 2017
The official description for our job opening that I mentioned last week is shown below.
Anyone can contact me at damartin at synopsys.com<mailto:damartin at synopsys.com> <snip> if they have any questions. Thanks!
Job Opening at Synopsys:
Analog Design Engineer, Sr I
You will be part of an R&D team developing high speed analog and mixed-signal integrated circuits for 10+ Gbps SerDes IP. We are looking for an engineer with theoretical knowledge and practical experience to contribute to the team. You will work with a cross functional design team of analog and digital designers from a wide variety of backgrounds. Our design environment is best-in-class with a full suite of IC design tools, supplemented by custom in-house tools, and supported by an experienced software/CAD team.
The job site is in Hillsboro, OR in the suburbs of Portland.
* Review SerDes standards to develop analog sub-block specifications.
* Identify and refine circuit architectures to achieve optimal power, area and performance targets.
* Propose design and verification strategies that efficiently use simulator features to ensure highest quality design.
* Oversee physical layout to minimize the effect of parasitics, device stress, and process variation.
* Present simulation data for peer and customer review.
* Document design features and test plans.
* Consult on the electrical characterization of your circuit within the SerDes IP product.
* PhD with 1 year, or MSc with 3 years of analog IC design experience.
* In depth familiarity with transistor level circuit design - sound CMOS design fundamentals.
* Detailed design experience with at least one, and familiarity with several other SerDes sub-circuits:
* receive equalizers, samplers, voltage/current-mode drivers, serializers, deserializers, voltage-controlled oscillator, phase mixer, delay-locked loop, phase locked loop, bandgap reference, ADC, DAC
* Aware of ESD issues (i.e. circuit techniques, layout).
* Familiarity with custom digital design (i.e. high speed logic paths).
* Knowledge of design for reliability (i.e. EM, IR, aging, etc.).
* Knowledge of layout effects (i.e. matching, reliability, proximity effects, etc.).
* Experience with tools for schematic entry, physical layout, and design verification.
* Hands-on experience with physical layout of high speed circuits is a plus.
* Knowledge of SPICE simulators and simulation methods.
* Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture.
* Experience with TCL, Perl, C, Python, MATLAB, or other scripting languages is desired.
* Good communication and documentation skills.
David A. Yokoyama-Martin, aka David A. Martin
Synopsys, Inc. damartin at synopsys.com<mailto:damartin at synopsys.com>
-------------- next part --------------
An HTML attachment was scrubbed...
More information about the Eecs-news-links