[Eecs-news-links] FW: Full Time Position In MediaTek
tina.batten at oregonstate.edu
Thu Sep 22 15:20:16 PDT 2016
From: Amr Elshazly [mailto:shazlys at gmail.com]
Sent: Thursday, September 22, 2016 9:36 AM
Can you please help posting this to OSU grad students (ECE/ analog-mixed signal groups).
Any one interested, to email resume to “Tamer Ali” <Tamer.Ali at mediatek.com<mailto:Tamer.Ali at mediatek.com>>
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Can you help me forwarding this to OSU?
Senior/Staff Engineer at MediaTek Irvine
1- Architecture study and evaluation of advanced Serdes topologies
2. Serdes design of different blocks including, but not limited to, drivers, front ends, samplers. comparators, ADCs, DACs, PLLs, clock distribution..etc
1. MS or above with major in EE or Physics related field.
2. Familiar with serial links and wireline transceivers design and verification.
3. Familiar with Cadence design tools.
4. Excellent working attitude and good interpersonal and communication skills.
The project is in early stages of development, so hired designers will get a great opportunity to learn and gain experience through the difference design phases and interaction with industry veterans and expertise.
If you are interested email your resume to “Tamer Ali” <Tamer.Ali at mediatek.com<mailto:Tamer.Ali at mediatek.com>>
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