[Eecs-news-links] Microprocessor/SoC Debug Engineer @ Intel

Batten, Tina tina.batten at oregonstate.edu
Thu Nov 14 17:01:03 PST 2013



-------- Original Message --------
Subject:

Fwd: Recruiting

Date:

Tue, 12 Nov 2013 09:43:30 -0800

From:

Ethan Minot <minote at science.oregonstate.edu><mailto:minote at science.oregonstate.edu>





<snip>
  Here is a nice job opportunity at Intel. Josh Kevek is the "insider" who will help promote OSU candidates.

- Ethan


-------- Original Message --------
Subject:

Recruiting

Date:

Mon, 11 Nov 2013 20:00:42 +0000

From:

Kevek, Joshua W <joshua.w.kevek at intel.com><mailto:joshua.w.kevek at intel.com>

To:

minote at science.oregonstate.edu<mailto:minote at science.oregonstate.edu> <minote at science.oregonstate.edu><mailto:minote at science.oregonstate.edu>

CC:

Duggirala, Rajesh <rajesh.duggirala at intel.com><mailto:rajesh.duggirala at intel.com>




Ethan,

Any chance I can get you to distribute this to the physics department? And maybe also get Conley or someone to distribute it in EE? Our group is trying to grow pretty quickly.

Thanks!

Josh

Contact for interested candidates: rajesh.duggirala at intel.com<mailto:rajesh.duggirala at intel.com>


*Sr. PTD Mod/ IDY Engineer-  Microprocessor/SoC Debug Engineer*

_Job Description_

- Play critical role in Intel's industry leading next-generation semiconductor process technology development by debugging fails in leading edge microprocessors and SoC's to isolate defects induced either because of process development experiments or process excursions.

- Interface with Portland Technology Development (PTD) Yield Engineers to understand the distribution and relative importance of various fails, perform debug on fails to isolate defects on die using a variety of test and characterization techniques, and interface with PTD Failure Analysis Engineers to visualize the defects, so PTD Integration Engineers can drive the reduction of the defects in the process

- Own development and sustenance of debug electrical, analytical test and characterization systems and equipment

- Develop and enable debug of leading edge microprocessors and SoC's by driving the insertion of next generation design for manufacturing and testing (DFx) circuitry into future microprocessors and SoC's designs and related test content and collateral development

_Qualifications:_

PhD in Electrical Engineering

Hands-on experience in a laboratory preferred

No prior experience with Debug is needed. As long as candidates have background in Digital CMOS acquired through graduate level courses at least, the training provided on the job should suffice to excel and contribute to Intel's process technology development efforts.

_Job Primary Location:_

Portland, OR
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