[Eecs-news-links] Job opening @ Intel
tina.batten at oregonstate.edu
Sun Apr 28 19:59:06 PDT 2013
From: Adrian, Marshall J [mailto:marshall.j.adrian at intel.com]
Hi OSU Friends,
I have a request for you. I need to hire somebody to work on my team at Intel ASAP! Could you please pass the word around that I have a job opening that needs to be filled.
Resumes should be sent directly to me. I am looking for a recent undergrad/grad graduate.
Below is job rec.
This position is for a Design Automation (DA) Engineer within the Intel Architecture Group, Knights Corner and Knights Landing multi-core CPU projects.
The applicant will be responsible for development, deployment, and support of the validation model builds and release flows with an emphasis on RTL integration, Logic Verification and automatic IP generation and component automation. The successful candidate required to understand software build flows as well as different revision control system. The position will require close collaboration with RTL design and validation staff, as well as members of the DA team. In this position, candidate will start some methodologies and flows from scratch as well as improve and monitor existing flows for further enhancements.
Minimum Requirements (Please specify # of years required):
Education: Bachelor of Science in EE/CS
- 3+ years experience with software and RTL simulation environment
- Experience writing automation code and scripts using Perl, Python, C, C++
- Working knowledge of database concepts as wells as web programming ( mainly PHP/HTML/SQL).
- Strong understanding/experience with revision control system ( preferably Git and Bit Keeper)
- Experience at least with one HDL language
- Strong problem-solving skills
- Good communication skills and strong customer orientation are a must since design team is spread across multiple sites
Preferred Requirements (nice to have):
Education: Master of Science or Ph.D. in EE/CS
- 5+ years experience with software and RTL simulation environment
- Experienced with Specman and/or system Verilog Test bench languages
- Computer architecture and micro-architecture knowledge
If you have any questions let me know! Thanks!
VPG Silicon Design Architect
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